module top;
wire x_in1 ,x_in2 ,x_in3 ,x_in4;
system_clk #50 clk1(x_in4);
system_clk #100 clk2(x_in3);
system_clk #200 clk3(x_in2);
system_clk #400 clk4(x_in1);
and4_rtl cl (y_out ,x_in1 ,x_in2 , x_in3 , x_in4);
endmodule


module and4_rtl(y_out ,x_in1 ,x_in2 ,x_in3 ,x_in4 );
input x_in1 , x_in2 , x_in3 , x_in4;
output y_out;
assign y_out = x_in1 & x_in2 & x_in3 & x_in4;
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule